Microprocessors typically employ a branch prediction unit to make a prediction of whether a branch instruction will be taken during execution of the instruction, and to predict the target of a predicted-taken branch. The branch predictions improve flow and reduce the likelihood of forming bubbles in an instruction pipeline. Specifically, by making a branch prediction, the microprocessor does not have to wait until a branch instruction has passed the execute stage of the pipeline before the next instruction can enter the fetch stage in the pipeline. The branch prediction unit predicts whether a conditional jump is most likely to be taken or not taken. The instructions at the predicted target of the branch is then fetched and speculatively executed. If the branch prediction is correct, the instruction pipeline continues to execute instructions while reducing the likelihood of creating bubbles in the pipeline, and the performance of the pipeline is increased. On the other hand, if the branch prediction is incorrect, then the speculatively executed or partially executed instructions are discarded and the pipeline starts over with the correct branch target incurring a delay.
In one example implementation, a branch prediction unit is powered up in parallel with an instruction cache when an instruction fetch is performed. The branch prediction unit is powered up to look up a branch prediction for the instruction data being fetched from the instruction cache. In other words, every time instruction data in the instruction cache is looked up, the branch prediction unit is also powered up.
However, there are various limitations with this approach for controlling the branch prediction unit. For example, in cases where an instruction fetch is performed on a cacheline that was previously fetched from the instruction cache, and the fetched instruction data contains no branches, the power consumed to look up the branch prediction in the branch prediction unit is wasted, because the instruction data does not include a branch instruction. In other words, in this approach the branch prediction unit is powered up during every instruction fetch operation regardless of whether the fetched instruction data does or does not include a branch instruction. Accordingly, this approach for controlling the branch prediction unit generates unnecessary power consumption, when the branch prediction unit is powered up for instruction fetches of instruction data that does not include a branch instruction.